A week of SSD, NAND questions and New Technology

It’s hard to believe that it’s been 20 years since the invention of flash memory, but the 20-foot timeline documenting its milestones that was displayed at this year’s Flash Memory Summit offered ample evidence of the progress the technology has made. Attendance at this third Summit once again broke records set by previous shows and the energy of the attendees was high. At more than 1,300 registered attendees, 2008 was at least 25% larger than 2007. Having been a sponsor since the show’s inception, we can confirm that it was even more packed this year. Most of the keynote presentations spilled out of the main hall, and people were stacked up into the hallway trying to hear what was being said inside. The quality of the presentations once again proved worth the trip to Santa Clara, but it was obvious to everyone that the show is quickly outgrowing the Santa Clara Marriott.

The unofficial theme this year appeared to be solid-state drives (SSD), but beyond the SSD buzz, there were many presentations on designing NAND-based products, software optimization of flash, future technologies, and other flash-related topics of interest. Datalight gave four presentations (Flash Interfaces 101), and organized a forum on using flash in embedded as well as a full-day “executive update.”

There were a couple of keynote addresses we found particularly interesting and entertaining:

Dean Klein from Micron gave a speech entitled, “A Closer Look at NAND Flash.” Highlights of Dean’s keynote included a map of NANDs progress through the Gartner Cycle of Hype,

 

Gartner Cycle of Hype – Source: Gartner Research

in which he asserted that NAND is over the “peak of inflated expectations,” heading down into the “trough of disillusionment.” Klein jokingly referred to hard-drives several times as “rotating rust,” and the address featured an entertaining series of video clips along the lines of Apple’s Mac vs. PC ads, in which Hard Drive was escorted by Flash to a therapy session to talk about his sluggishness, forgetfulness, narcolepsy, and overeating (power consumption).

Eli Harari from SanDisk gave a keynote called “Changing the World: The Flash Memory Revolution.” Eli’s speech was less humorous than Dean’s, but no less interesting to listen to. He showed several timelines describing the evolution of flash applications, and a chart predicting that NAND demand will outstrip supply by 2011, allowing flash vendors to raise prices (!) and finally get a return on their investment in the technology. He also compared the progress of NAND density to Moore’s law, showing that NAND is tracking far ahead of where Moore’s law says it should be. He theorized that the next flash technology will be 3D NAND, and gave a fascinating demonstration of how it’s built and how it works, including photographs of 3D NAND’s unique architecture.

Spansion showed their ecoRAM: basically flash in a DIMM form factor. Cool. And eco-friendly, apparently. This new class of flash promises to reduce the power requirements for large server applications, using an eighth of the energy of DRAM, with better reliability, and read performance fast enough to meet the rapid access requirements of large-scale server installations.

Which highlights another key theme of the Summit: Power. How can flash help reduce global warming? Can SSDs make data centers run more economically? Uh, did I say “data centers?” Yes, surprise! While last year’s Summit saw the invasion of the laptop, this year a significant portion of the sessions addressed opportunities in the Enterprise segment.

But the “Big E” didn’t totally eclipse the “Little e” (embedded). There is still a growing need for low power, high performance flash soldered onto boards and into removable cards for embedded systems. The embedded track had presentations ranging from the basics of flash interfaces and differences between NOR and NAND to complex design methodology and frequency sources for flash memory applications.

Speaking of last year’s Summit, where Hybrid Hard Drives (traditional hard disk drive with flash caching) battled SSDs for attention, whatever happened to the HHDs? The only sign of them we saw was a presentation from Seagate wherein they said there is still work to do, particularly on the software (i.e., Windows Vista).

Our take overall? Industry insiders’ perspectives are essential for long term planning and this show is the place to get them. But all that crystal-ball-gazing can be a bit out of phase with where customers are today. SSDs are interesting and undoubtedly will be a key component in many future designs, but the reality is that migration from NOR-only systems to those that include both NAND and NOR or just NAND continues to be the mainstay for today’s designs. An analyst from IDC cashed a reality check on the SSD hype when he put up a slide showing relative market sizes of flash memory (big), hard disk drives (huge) and SSDs (tiny).

While many flash manufacturers are in an oversupply situation on NAND, others have parts on allocation. The industry as a whole is looking for ways to reduce costs and keep (or get) fabs profitable. This causes lower volume, lower margin product lines to be discontinued, sometimes just as designs using them are about to go to market.

Bottom line? The Flash Memory Summit provides a great opportunity to step outside our day-to-day reality and consider the possibilities promised by emerging technology. Next year’s Summit is sure to be a must-attend event for gaining planning perspective. We hope to see you there!

If you missed the Summit, presentations should be available soon at www.FlashMemorySummit.com. Bill’s presentation on flash interfaces, complete with narration, is available now: Flash Interfaces 101

Contrary to popular belief, flash memory does not last forever. Every flash part in existence comes with a finite number of write and erase cycles before the data stored becomes corrupted and the flash part unusable. Most flash file systems on the market today include a basic type of wear leveling, but all wear leveling algorithms are not created equal. Chiefly, wear leveling strategies can be broken into two camps: Dynamic wear leveling monitors high and low-use areas of the flash, and after a certain set point, will swap out high-use erase blocks with low-use erase blocks. Large areas of a disk may be occupied by rarely-changing data, forcing frequent system writes/erases to occur on the remainder of the disk and increasing the wear on those areas. Static wear leveling deals with this by moving static data to higher-use areas of the flash, thereby balancing the load. The idea system would use both kinds of wear leveling. Check out some real-world examples by reading our whitepaper on the topic:

A Short Study on Wear‑Leveling

Over the past fifteen years, flash memory has been widely adopted in mainstream consumer grade products having short lifetimes, often measured in months. In recent years however, flash memory has begun to break into more industrial and commercial grade devices with lifetimes counted in years. There are many unique characteristics of flash memory that have fueled its growth across these varying market segments, such as its ability to retain data without continued power; this benefit, however, comes at a cost of a finite lifetime and endurance. The hardware architecture and software technologies that extend the life of a flash chip are often ill‑considered or, at times, given more worry than necessary. While the limited lifetime of flash memory may or may not be problematic for products that are expected to last ten or more years, flash management software can expand the breadth of available flash parts for your project.

This paper focuses on determining when the limitations of flash memory lifetime become significant and what can be done about them.

Flash Lifetime Metrics

Flash memory lifetimes are described in two primary metrics which are generally touted on the first page of any flash memory manufacturers’ data sheets:

• Data retention
• Endurance cycles

Data retention is often listed at 20 years at a given operating temperature. Increased temperature ranges reduce the data retention period which further decrease as the flash memory is used at or near its specified operating temperatures. It is important to note that data retention is measured from the time data is successfully programmed.

The second metric, endurance cycles, is a measure of the number of write and erase cycles that the flash memory can endure before becoming unreliable. Flash memories are organized into a number of erase blocks or sectors and each must be erased prior to writing data. A typical erase block is 128KB in size, however may range from 512B to 2,048KB or even more. Any given address within an erase block cannot be rewritten without an intervening erase. Erase cycles are cumulative and affect only those erase blocks being cycled. In other words, an error in any erase block is constrained to the data of that block.

Erase cycles range from 1,000 to 1,000,000. While these ranges have an order of magnitude difference, it is the application the flash is placed into that will primarily define the product lifetime.

What is Wear-Leveling?

Wear‑leveling is a process to ensure that an entire flash memory device or an array of devices is used in a uniform fashion in order to extend the overall lifetime of the flash.

For a simplistic example of wear-leveling, let’s look at a data recorder device with the following characteristics:

• Application: The device collects and stores the past 24 hours of field data by simply writing and rewriting the data to the same location on the flash.
• File size of data to be recorded: 128KB
• Erase block size (of the flash): 128KB
• Flash memory endurance: 1,000 cycles

With one spare area, the device is assumed one cycle per day each year:

(1,000 cycles ÷ 365 days) * 1 spare area = 2.74 years

In this example, it would take about 2.74 years to cycle that one erase sector 1,000 times.

For the data recorder device to accommodate the write‑erase rules of flash memory, it would have to complete an erase operation to start writing the next day’s set of data. To make the data recorder more robust – to ensure that it doesn’t lose a whole day’s worth of data – we can set aside a second erase block, and erase the first block only after the second set of data was recorded. The resulting side effect is the introduction of a simple wear-leveling scheme.

With two spare areas, the device is assumed one cycle every two days each year:

(1,000 cycles ÷ 365 days) * 2 spare areas = 5.48 years

With these parameters, the period of time prior to cycling the flash to its lifetime has just been increased to almost 5.5 years!

This simple example shows how distributing a fixed set of writes across more flash sectors can increase the period of time prior to cycling the flash to its specified limits. The following sections describe how to account for the important variables associated with wear-leveling techniques, and determine the expected lifetime of the flash in any application.

Continue: A Short Study on Wear-Leveling

Consumer electronics and embedded software devices are using larger amounts of flash memory for nonvolatile storage than ever before. So what kind of flash memory should you use? The choice between using NAND and NOR Flash may not be a simple one for the complex embedded devices being developed today. While ever-larger media files are driving increased demand for inexpensive NAND, powerful new operating systems and intricate applications running on fast processors ask for the fast-executing code NOR can support.

Read Datalight whitepaper Choosing NAND or NOR Flash Memory: Tradeoffs and Strategies to Learn More

Consumer electronics and embedded software devices are using larger amounts of flash memory for nonvolatile storage than ever before. One important decision in designing such devices is what kind of flash memory to use: NAND or NOR?

NOR flash memory has traditionally been used to store relatively small amounts of executable code for embedded computing devices such as PDAs and cell phones. NOR is well suited to use for code storage because of its reliability, fast read operations, and random access capabilities. Because code can be directly executed in place, NOR is ideal for storing firmware, boot code, operating systems, and other data that changes infrequently.

NAND flash memory has become the preferred format for storing larger quantities of data on devices such as USB Flash drives, digital cameras and MP3 players. Higher density, lower cost, and faster write and erase times, and a longer re-write life expectancy make NAND especially well suited for consumer media applications in which large files of sequential data need to be loaded into memory quickly and replaced with new files repeatedly.

The choice between using NAND and NOR Flash may not be a simple one for the complex embedded devices being developed today. While ever-larger media files are driving increased demand for inexpensive NAND, powerful new operating systems and intricate applications running on fast processors call for the kind of fast-executing code NOR can support. An important example is a smart phone or PDA that combines a tremendous need for storage with a demanding set of application performance requirements. In some cases an optimal design might call for both types of flash memory in the same device.

Whichever type of flash is used in a device, there are certain negative performance characteristics that need to be mitigated. NOR is fast to read current data but markedly slower to erase it and write new data. NAND is fast to erase and write, but slow to read non-sequential data through its serial interface. NAND is also prone to single-bit errors, requiring rigorous algorithms for error detection and correction.

Well-designed software strategies can be very effective in increasing the performance and reliability of Flash hardware. The goals of flash memory management software include:

Avoid loss of data. Perhaps the most important goal in managing flash memory is to assure that no data is ever lost as a result of an interrupted operation or the failure of a memory block. There are several ways that flash management software can achieve this goal. Rewrite operations, for example, can be managed in such a way that new data is written and verified before the old data is deleted, so that no power loss or other interruption can result in the loss of both old and new data. Bad block management is another important safeguard to prevent data being written to memory blocks that have failed. Software can check for bad blocks shipped from the factory, as is typical with NAND, and avoid writing to those blocks from the beginning. When blocks go bad over time they can be identified and managed so that they are no longer used. Finally, as the end of media life nears, good memory management software can implement a graceful strategy such as placing the entire flash unit in a read-only state, thereby avoiding data loss when the number of block errors exceeds a predefined number.

Improve effective performance. Two ways media management software can improve performance are background compaction and multithreading. Compaction reclaims space by identifying blocks that have obsolete data that can be erased, copying any valid data to a new location, then erasing the blocks to make them available for reuse. Such compaction increases the amount of usable space on the media and improves write performance. Compaction may also help to defragment noncontiguous data for improved performance on read operations. The space recovery is particularly valuable for the more costly NOR memory and the defragmentation benefits the slower-reading NAND. Compaction is best performed in the background during idle time, however, or it can interfere with critical operations and degrade performance. This is where a multithreading system becomes important. By allowing high-priority read requests to interrupt low-priority maintenance operations, a multithreading system can reduce read latency by orders of magnitude compared to a single-thread solution.

Maximize media lifespan. When some blocks of memory contain fixed content, such as binary code, the remaining blocks will experience increased demand for erase and write operations, leading to earlier failure. Wear-leveling algorithms can prevent overuse of memory blocks and prevent a “stalemate” scenario in which a small region of memory becomes locked in a pattern of repeated writing and compaction. Wear leveling software can monitor block usage to identify high-use areas and low-use areas containing static data, then swap the static data into the high use areas. It can also balance write operations across all available blocks by choosing the optimal location for each write operation.

The decision between NAND and NOR memory will ultimately depend on both technical and pricing requirements of the device being built. Whatever type or combination of flash is used, it is prudent to include memory management software to prevent data loss while improving the performance and maximizing the lifespan of the memory.

The read, write and erase timing characteristics of flash hardware specifications are useful for comparing different products, but don’t tell the whole story about what you will get from your real-world devices. When Flash memory is incorporated into a system, the performance of the system depends on a number of factors. One key factor that can reduce the effective performance of flash memory involves the shared bus topology of your system. Optimal flash performance depends on the speed and availability of the bus that connects the flash to the system. Also critical are the manner in which the operating system handles interrupts and whether the flash device is connected to the system’s interrupt architecture.

The published read, write, and erase timing characteristics of flash hardware specifications are useful for comparing different products, but don’t tell the whole story about what you will get from your real-world devices. When Flash memory is incorporated into a system, the performance of the system depends on a number of factors in addition to the capabilities of the flash hardware.

One key factor that can reduce the effective performance of flash memory involves the shared bus topology of your system. Optimal flash performance depends on the speed and availability of the bus that connects the flash to the system. For example, if your flash shares a bus with parts that operate at slower clock speeds, the timing of the accesses to the flash part may be extended to match. On the other hand, your flash part may be competing for bus availability with other demanding high-speed system components.

RAM memory, network interfaces, and LCD screens are demanding components that can compete with flash for bus and CPU bandwidth. The use of certain features of the processor and operating system, such as DMA and caching, can have a similar impact. As more components, peripherals, and device drivers are added to the system, more opportunities arise for the bus to be shared. The proliferation of high performance audio and video features, now common on mobile devices, can further tax a shared bus system on a general purpose chipset. For this reason special-purpose chipsets designed for a specific application, as well as tuning the characteristics of your flash management software to meet your specific needs, will generally enable higher levels of flash performance.

Well designed hardware bus topology can alleviate the issue of shared bus contention, yet other factors may still impact flash memory performance. Even if the flash part has full speed access to the processor’s external bus, the availability of the CPU to service that bus is still a question. Bus arbitration may take CPU cycles away from the flash bus in favor of other system busses or internal accesses. Operating system timer interrupts and other peripheral device driver interrupts can interfere with flash software operations, as can a CPU that is simply overloaded by running complex applications.

Also critical are the manner in which the operating system handles interrupts and whether the flash device is connected to the system’s interrupt architecture. Some flash is connected to processors in such a way that the signal generated by the flash is connected to a GPIO, or not connected at all. This may have little impact on flash performance, but it will limit the ability of the CPU to execute other flash-related software, such as garbage collection, or even unrelated tasks. Additionally, many systems have an explicit or implied interrupt priority that must be considered at the system level. Responsiveness requirements of all interrupt-driven components in the system must be carefully weighed against the desire to maximize flash performance.

An equally significant factor affecting flash performance that might be easily overlooked is the flash management software itself. There is a necessary amount of overhead inherent in running software to manage your flash memory, and there are some complex operations that the software needs to accomplish well in order to optimize flash performance. The software provided by your flash vendor may or may not provide satisfactory performance for your particular application.

While flash memory often appears to the end user like a virtual hard drive, the underlying technology is quite different and presents certain challenges. Flash management software can do more than bad block management and wear leveling, it can increase the effective performance of the flash part by addressing these challenges:

1. Flash performance can be impeded by the need for a slow erase operation before writing new data, but software that intelligently performs background garbage collection during idle time can solve that problem.
2. Fragmented data can degrade performance in applications such as streaming media from NAND memory, but compaction software that de-fragments the data can improve performance in these situations.
3. With some algorithms, throughput is maximized for performance until a percentage of the flash memory is used, at which point performance can degrade. The percentage of the flash that is used before performance suffers can be tuned in some implementations, by allowing the system designer to reserve a specified amount of ‘cushion’ of unused memory.
4. In some solutions, maintenance operations such as garbage collection can preempt high-priority read requests. Implementations that make careful use of multithreading operating systems’ capabilities to manage this issue can reduce read latency by orders of magnitude.

Several factors will affect the performance of flash memory in your real-world system, some of which may be beyond your control. Chipset hardware and system bus topology decisions may have been made already. No matter whether your hardware is specially designed for your application or you are using a general-purpose hardware design, though, the effective performance of your flash memory can be improved through software methods. Datalight FlashFX is a multithreading memory management software solution that enables garbage collection, data compaction, memory cushion, and high priority read interrupts to allow the highest real-world flash performance your hardware configuration can support.

Linux has been slowly but surely establishing itself as the predominant OS in the embedded industry. ABI research report suggested that 23% of Smartphones will be based on Linux by 2013. High-profile industry support from Android and the LiMo foundation has put the spotlight back on embedded Linux.

In a previous post, we talked about flash memory and the various layers of flash management. In this post, I will talk about JFFS2, the most popular flash file systems available on the Linux platform

JFFS2

The Journaling Flash File System version 2 (JFFS2) is a log-structured file system that was originally designed in 1999. The original JFFS was developed by Axis Communications (and later enhanced by Red Hat) to provide support for NOR flash devices. The current version has been updated to include support for NAND flash. JFFS2 is open-source software, distributed under the terms of GPL license.

JFFS2 Strengths

1. Portability to Development Environments: Included with the Linux kernel since version 2.4.10, JFFS2 has become a de facto standard flash file system for Linux developers. Today, it is included in most commercial Linux distributions (such as MontaVista and Wind River Linux). Because of this wide distribution and use, it has been integrated into many varying environments and is known to be relatively easy to build.

2. Reliability: As changes are made to the file system, a “log” is built; this log provides information about where a file and its associated metadata are located on the flash chip.^[1] As the log is consistently maintained, it will be read back in the event of an unexpected power loss to determine the location of a missing file. Although the log structure provides a level of data reliability, this is accomplished at a cost to performance

3. Support for disk-wide compression: The benefit, or cost, of using compression depends on each specific use case. Compression will be useful in making efficient use of disk space when several text-only or code data (OS, etc.) files are being stored. Media files are already compressed (in *.jpg, *.mpg, or other formats), so the time used to attempt data compression is wasted. It is even possible that media files may take up more space after an unnecessary compression than originally needed. Disk usage and performance for the type and number of files to be maintained must be considered by the device designer in order to determine whether compression will yield a benefit or not

JFFS2 Shortcomings

1. Resource usage: RAM usage by JFFS2 increases in linear proportion to the number of nodes. Hence on large flash volumes, the system resources required by JFFS2 can be very significant

2. System performance: For devices that primarily use the file system for read operations, JFFS2 performance may be acceptable. However, for multi-functional devices whose applications perform a continuous mix of read and write operations, it is likely that the performance of a system using JFFS2 will not pass a rigorous standard. In addition to slow writes, the flash disk mount times of JFFS2 are exceptionally slow and worsen as the amount of data stored increases. Upon start-up after an unexpected power failure, JFFS2 must reconstruct the file system structure from the log. This is a costly operation that requires several seconds – more for volumes that are large or near-capacity. The device will be halted during this check operation, as any data that is stored on the disk will not be ready for use until the start-up completes

Informative links on JFFS2

1. JFFS2 Technical paper [PDF]

2. JFFS2 RAM usage [ppt] – Presentation at Embedded Linux Conf 2007

In the next post in this series, we will look at another popular Linux flash file system – YAFFS.

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[1] Details on JFFS2 log structure can be found here http://sourceware.org/jffs2/jffs2-slides-transformed.pdf

NAND flash is everywhere these days. The iPod Nano, usb flash drives and various other flash card-based devices like GPS navigators, digital cameras and smart phones have brought high-density NAND to the mainstream. What most users don’t realize however, is that NAND storage, though “solid-state,” relies on a fragile and inherently-flawed technology to store all those bits and bytes. Enter the NAND controller, a relatively small piece of software that renders NAND errors virtually invisible to the end user, making your iPod and other devices work like a champ. To learn more about NAND controllers, read our whitepaper on the topic:

An Overview of NAND Flash Memory Controllers

The demand for NAND Flash memory is growing at a phenomenal rate. In 2005, worldwide revenue for NAND Flash rose to $10.8 billion, up 60% from 2004. The inclusion of NAND Flash in an increasing number of MP3 players, high-end cell phones, and digital cameras has fueled expectations that NAND will overtake NOR in a number of markets. Rapid increases in the capacity of NAND Flash, coupled with mobile consumer products that demand ever-increasing amounts of data storage, lay out a very bright future for this technology in the coming years.

What is NAND Flash?

NAND Flash is a form of non-volatile memory introduced by Toshiba and Samsung in 1989. Its benefits include high storage density, fast access times, low power requirements in operation, and excellent shock resistance. These benefits are tempered somewhat by the inherent limitations of the technology:

• Due to production yield constraints, NAND Flash ships from the factory with a number of bad blocks that cannot be used.
• NAND Flash has a serialized data interface similar to a hard disk and so cannot be used for execute in place functionality, such as running code directly from the chip.
• Over time and after multiple erase cycles the memory will tend to “wear” and become less reliable.
• The bits stored in the chip can sometimes flip - or reverse - from 0 to 1 or vice versa.

Over time, NAND Flash technology and software has evolved to the point where these limitations are invisible to the end user. Owners of iPod Nanos do not overly concern themselves with bad blocks or bit-flipping.

What does a NAND controller do?

Increased Performance

Approximately 3% of the overall flash array is reserved as a “spare area” in order to cope with flash vulnerabilities, like bit-flipping and bad blocks. Approximately 3 to 6 bytes in the spare area are reserved for error detection and correction algorithms, while the remainder of the spare area is used for remapping bad blocks. Without a NAND controller the algorithms that handle these functions would be executed by the general purpose CPU. However, NAND controllers are available that will perform these functions in hardware. This reduces the CPU load on the device which has the effect of increasing battery life as well as increasing performance – both important factors in mobile technology. In addition, the advent of Multi-Level Cell (MLC) NAND Flash Technology requires even more rigorous error detection algorithms due to the increased chance of an error occurring. A NAND controller is perhaps the only reasonable way of performing this task.

NAND controllers can implement read and write caching and transfer data to and from the NAND Flash chip independently of the general purpose CPU. This increases the overall throughput and can again reduce the load on the system.

Faster Integration

The serialized data interface to NAND presents a difficult scenario for transferring data in and out of the chip. Unlike other memory technologies, like NOR or DRAM, an address must be fed in a bit at a time, at just the right time, and then read or write the actual data in a similar fashion. A NAND controller encapsulates the interface with the NAND chip and handles this communication, thereby presenting an effortless interface to the user.

The lack of standardization among NAND Flash manufacturers has been problematic throughout its brief history. The use of NAND controllers allows some flexibility in the choice of a NAND Flash chip as any given controller will support a range of NAND chips. Changes in NAND Flash, therefore, will not necessarily require a change in NAND controller or software.

Integrated NAND Controllers

Integrated NAND controllers are growing in popularity as mobile processor vendors, such as Freescale and Texas Instruments, build NAND controllers directly into their processors. The advantages of this approach are that the design can be kept small and the costs can be minimized. The disadvantage is the inevitable delay between a new NAND Flash technology appearing and the release of an integrated processor that supports it.

A dedicated, or external, NAND controller is one in which the NAND controller is a separate chip that can be sourced independently of other parts. The advantage of choosing a dedicated NAND controller is the wide range of latest and greatest NAND Flash chips available. This is due to the relatively short time to market for a chip with this level of complexity. The disadvantage of using a dedicated NAND controller is that chip uses additional PCB space and will cost more money than the integrated approach.

Specialized NAND Controller Software

The diagram below shows an overview of the interaction between the embedded application, file system, Flash management software, NAND controller, NAND controller driver, and the NAND Flash memory chip.

NAND Controllers require specialized software to hide the unpleasant details of the NAND controller and NAND Flash itself and presents the user with a clean and highly usable interface to the memory.

At a higher level, the NAND controller driver is often utilized by an intelligent block device driver, such as FlashFX Pro from Datalight, or a flash file system. Some important functions of this software are:

• Reducing the integration time for developers of embedded applications.
• Handling bad blocks present on the NAND Flash chip.
• Providing small block emulation, which is required due to the relatively large “erase blocks” present on NAND Flash.
• Mitigating the effects of wear on the NAND flash through the application of wear leveling algorithms that spread writes and erases over a wider area.
• Providing a file system interface that allows you to interact with the Flash chip at the file level.

Summary

The strong desire for more storage and better performance in consumer devices has elevated the pressure on NAND Flash and introduced new technologies like NAND Controllers to device engineers.  In order for new flash technologies to be adopted, it is critical that the enabling software also continues to evolve.

Flash memory has established itself as the technology of choice for device data storage on embedded devices. The advantages it brings in terms of storage capacity, I/O throughput, power consumption and board space savings are significant. In 2007, flash memory was a $7.7 billion industry. Analysts predict a 23% growth of the flash memory market between 2007 and 20111; surpassing the history-making growth of DRAM ten times over.

One of the barriers to flash memory adoption is its perceived complexity of integration into a product design. With the flash memory market branching to multiple product lines beyond traditional NAND and NOR devices, this perception, along with a concern about the reliability of flash, is becoming magnified. Basic flash management software can lessen the complexity of integration, and sophisticated flash software can ensure the optimum lifetime and reliability of a flash device.

The challenges of integrating flash memory are broad, including operations from the seemingly simple – like reading, writing, and overwriting data – to the exceedingly complex – such as bad block management and wear-leveling. When flash memory is not accompanied by an intelligent software manager, the system will suffer from slow reads and writes, data corruption, and a short usable life.

There has been a lot of interpretations for the term “Flash File System”. Some consider it as the combination of flash management software and a block file system. For some it is just the flash management piece. The following diagram shows the different layers involved in managing data on flash memory and the corresponding terminologies for software components

· Flash Driver: Basic software that provides rudimentary read/write access to flash; this software is often acquired from the chip provider, and is usually part-specific.

· Flash Manager: In addition to the functionality of a flash driver, a flash manager also intelligently determines which part is being used, and handles it accordingly – whether it is NAND, NOR, or a fusion of the two (i.e. Samsung OneNAND, or Spansion ORNAND). Bad block management, wear-leveling, garbage collection, and error detection and correction are features that a flash manager provides. A flash manager may also be designed to take advantage of unique performance or technical characteristics a specific part provides. Flash managers are sometimes referred to as FTL (flash translation layers).

· Flash File System: Contains the flash driver and the flash manager aspects, but also incorporates a file system that is designed for use with flash memory. In the way of performance optimizations, a flash file system includes a discard interface which ensures that erased blocks are immediately available for use by both the file system and the flash manager without additional queries to those blocks.

The following diagram shows the flash file system in perspective of an embedded device

Hope this post was useful in understanding the layers of flash management. In the next post in the series, we will look at various flash file systems for one of the most talked-about embedded OS – Linux.